Application Note 339 Fairchild's Process Enhancements Eliminate the CMOS SCR Latch-Up Problem In 74HC Logic

INTRODUCTION SCR latch-up is a parasitic phenomena that has existed in circuits fabricated using bulk silicon CMOS technologies. The latch-up mechanism, once triggered, turns on a parasitic SCR internal to CMOS circuits which essentially shorts VCC to ground. This generally destroys the CMOS IC or at the very least causes the system to malfunction. In order to make MM54HC/MM74HC high speed CMOS logic easy to use and reliable it is very important to eliminate latch-up. This has been accomplished through several layout and process enhancements. It is primarily several proprietary innovations in CMOS processing that eliminates the SCR. First, what is “SCR latch-up?” It is a phenomena common to most monolithic CMOS processes, which involves “turning on” a four layer thyristor structure (P-N-P-N) that appears from VCC to ground. This structure is formed by the parasitic substrate interconnections of various circuit diffusions. It most commonly can be turned on by applying a voltage greater than VCC or less than ground any input or output, which forward biases the input or output protection diodes. Figure 1 schematically illustrates these diodes found in the MM54HC/MM74HC family. Standard CD4000 and MM54C/ MM74C logic also has a very similar structure. These diodes can act as the gate to the parasitic SCR, and if enough current flows the SCR will trigger. A second method of turning on the SCR is to apply a very large supply voltage across the device. This will breakdown internal diodes causing enough current to flow to trigger latch-up. In HC logic the typical VCC breakdown voltage is above 10V so this method is more uncommon. In either case, once the SCR is turned on a large current will flow from VCC to ground, causing the CMOS circuit to malfunction and possibly damage itself. CMOS SCR problems can be minimized by proper system design techniques or added external protection circuits, but obviously the reduction or elimination of latch-up in the IC itself would ease CMOS system design, increase system reliability and eliminate additional circuitry. For this reason it was important to eliminate this phenomena in Fairchild’s high speed CMOS logic family. Characterization of this proprietary high speed CMOS process for latch up has verified the elimination of this parasitic mechanism. In tests conducted under worst case conditions (VCC=7V and TA=125 ̊C) it has been impossible to latch-up these devices on the inputs or on the outputs. In testing for latch-up, caution must be exercised when trying to force large currents into an IC. As with any integrated circuit there are maximum limitations to the current handling capabilities of the internal metalization, and diodes, and thus they can be damaged by excessive currents. This is discussed later in the test section. To enable the user to understand what latch-up is and how it has been eliminated, it is useful to review the operating of a simple discrete SCR, and then apply this to the CMOS SCR. Since most latch-up problems historically have been caused by extraneous noise and system transients, the AC characteristics of CMOS latch are presented. Also various methods of external and internal protection against latch-up is discussed as well as example test methods for determining the latch up susceptibility of CMOS IC’s.